This invention relates to a voltage sense circuit, and more particularly, to a circuit capable of sensing at a high speed a potential difference variation which develops between a pair of signal lines.
FIG. 1 shows a prior art voltage sense circuit of a RAM (randon access memory) composed of MOS transistors. In this voltage sense circuit, a pair of data lines 11 and 12 connected to memory cells included in the same column of a semiconductor memory array are connected to a power source V.sub.DD through p-channel MOS transistors T1 and T2 respectively. The transistors T1 and T2 are caused to conduct by a low-level (ground-level) chip enable signal CE, thereby precharging stray capacitances C1 and C2 associated with the data lines 11 and 12 to +V.sub.DD.
The data lines 11 and 12 are connected to output nodes 14 and 15 of a flip-flop circuit 13 through n-channel transistors T6 and T7 respectively, and have stray capacitors C3 and C4 between the source electrodes of the transistors T6 and T7 and ground respectively. The transistors T6 and T7 are adapted to precharge the output node capacitors C3 and C4 of the flip-flop circuit 13 to +V.sub.DD (+5 V) during the precharge period and to transmit to the output node capacitor C3 or C4 a potential change of the data line 11 or 12, which is caused by a data readout from an accessed memory cell of the memory cells connected to the data lines 11 and 12 and having the same Y-address, after the precharge period. To this end, the respective gate electrodes of the transistors T6 and T7 are supplied with a timing signal .phi..sub.1 having voltage levels of +8 V and +5 V as shown in FIG. 2. If the timing signal .phi..sub.1 is held at +5 V equivalent to the supply voltage +V.sub.DD during the precharge period, it is impossible to charge the stray capacitors C3 and C4 to +V.sub.DD. The capacitors C3 and C4 can be fully charged to +5 V by applying +8 V to the gate electrodes of the transistors T6 and T7.
After the precharge period, a memory cell is accessed, whereby the potential of one of the data lines 11 and 12 is somewhat lowered. This potential change is transmitted to the node capacitor C3 or C4 during a period of time when the timing signal .phi..sub.1 maintains +8 V. Consequently, the voltage across one of the node capacitors C3 and C4 is lowered. After the timing signal .phi..sub.1 has dropped to +5 V, the transistors T6 and T7 are turned off because the source-to-gate voltage of the transistors T6 and T7 becomes lower than the threshold voltage.
When a timing signal .phi..sub.2 applied to the gate electrode of a transistor T5 beccomes a HIGH level (+V.sub.DD), as shown in FIG. 2, the transistor T5 is turned on. As a result, a node capacitor holding a voltage lower than the supply voltage +V.sub.DD discharges to the ground level.
In consequence, one of the transistors T6 and T7 which is connected to the discharged node capacitor turns on to pull down the potential reduced data line to the ground level. That is, the transistors T6 and T7 also serve to pull down rapidly to the ground level the data line to which 0 (Low level) is read out from the memory cell.
Since the aforementioned voltage sense amplifier employs n-channel transistors for the transistors T6 and T7, the gate signal .phi..sub.1 requires a higher voltage level than the supply voltage +V.sub.DD. In order to produce a voltage level higher than the supply voltage, a level shift circuit is generally incorporated in a semiconductor chip in which the memory array is formed. If the transistors T6 and T7 are each connected with an additional n-channel transistor, the timing signal .phi..sub.1 may maintain the +5 level during the read cycle, and a timing signal applied to the additional transistors must have voltage levels of +0 V and +8 V. In this case, two power sources of +5 V and +8 V are required.
The necessity of the level shift circuit and the two power sources would render construction of the semiconductor memory complex, increasing the chip size and the number of terminals required.